1. Field of the Invention
This invention relates to semiconductor processing technology generally, and more specifically, to chemical mechanical polishing technology for planarization of deposited materials.
2. Description of the Related Art
The manufacture of an integrated circuit device requires the formation of various layers (both conductive and non-conductive) above a base substrate to form the necessary components and interconnects. During the manufacturing process, certain layers or portions of layers must be removed to form the components and interconnects. Generally, the removal is achieved chemically (etching), or chemically and mechanically (chemical mechanical polishing).
FIG. 1 is a simplified cross-sectional schematic of a semiconductor wafer, consisting of a dielectric layer 102 on top of a silicon wafer 104. Trenches are formed in the dielectric 102, using masking and etching techniques well known in the art. The dielectric 102 has a metal layer 101 deposited on top using techniques such as Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD) or electroplating. Copper is used in the metallic layer because of its inherent higher conductivity and improved resistance against electromigration, versus the prior art aluminum. The deposited metal fills the previously created trenches 103. The metal above the plane of the dielectric must be removed before subsequent steps in the device manufacturing process can be performed.
One method of removing the excess metal is through CMP as illustrated in FIG. 1. A slurry 105 containing abrasive particles (not shown) is introduced into a polishing device containing a polishing pad. The mechanical movement of the pad and abrasive particles relative to the wafer, combined with the chemical reaction of the slurry with the copper surface 107, provides the means for removing the exposed, oxidized surface of the copper layer 107. The chemical nature of the slurry used, along with that of the particles, depends on the type of material to be removed.
FIG. 2 illustrates the wafer of FIG. 1 after polishing. CMP of metals can be used to define vertical and horizontal wiring 203 in semiconductor wafers, such as a silicon wafer. This process requires high selectivity in removal rate of metals 203 versus dielectric surfaces 202, such as a silicon dioxide layer, to avoid both oxide erosion 206 on patterned structures and copper “dishing” 205, where dishing is defined as selective localized removal of the copper versus that of the surrounding oxide dielectric 202. This localized removal occurs because of differing hardness between the oxide dielectric 202 and the softer copper 203, and because the slurry is generally selected to preferentially remove the copper over the dielectric. Oxide erosion is also a result of the aforementioned reasons; in this case, however, narrow oxide features are less resistant to the induced abrasive forces than the wider oxide features because of the “dishing” of copper lines on either side of the oxide.
There are a number of ways of improving selectivity toward metals. Process parameters that are varied to improve selectivity toward metals versus dielectrics include reducing the polish pressure, optimizing the rotational and orbital speed of the polishing device, selecting the proper slurry chemistry, polish pad material, and polish pad groove geometry. However, all of these methods address the polishing side of the problem, rather than the material-choice issue for interlayer connects.
An alternative to changing processing parameters is to change the nature of the material polished. A problem associated with CMP of copper layers in semiconductors is related to the inherent softness of copper. If the copper could be hardened with little or no change in electrical or electromigration properties, process selectivity adjustments may be reduced or eliminated, thus improving process robustness and semiconductor device quality.
What is needed is an interlayer connect material for semiconductor devices that is harder than that used in the current art, allowing the use of the present polishing materials and methods, but resulting in better control of oxide erosion and dishing. This material should maintain close to the same conductivity and electromigration advantages associated with copper.